Presentation 2002/6/20
On the Circuit for Booth Recoder in Multiplier
Tetsuya INOUE, Atsushi TAMURA, Hiroyuki OCHI, Takao TSUDA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Booth selector consumes relatively large part of area and power dissipation in a Wallace-tree multiplier. This report proposes new Booth selector algorithms, Tamura method and Tei method. The former requires only 9 transistors for generating each partial product bit using pass-transistor logic SPL, and useful when area constraint is dominating. The latter requires 12 transistors for generating each partial product bit using transmission gate, and usable for low-voltage operation. In addition, it requires only 6 inputs for one partial product bit, which is effective for reducing congestion.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Booth Selector / Pass Transistor Logic / Low Power Dissipation / Multiplier
Paper # CAS2002-23
Date of Issue

Conference Information
Committee CAS
Conference Date 2002/6/20(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On the Circuit for Booth Recoder in Multiplier
Sub Title (in English)
Keyword(1) Booth Selector
Keyword(2) Pass Transistor Logic
Keyword(3) Low Power Dissipation
Keyword(4) Multiplier
1st Author's Name Tetsuya INOUE
1st Author's Affiliation Faculty of Information Sciences, Hiroshima City University()
2nd Author's Name Atsushi TAMURA
2nd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
3rd Author's Name Hiroyuki OCHI
3rd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
4th Author's Name Takao TSUDA
4th Author's Affiliation Faculty of Information Sciences, Hiroshima City University
Date 2002/6/20
Paper # CAS2002-23
Volume (vol) vol.102
Number (no) 161
Page pp.pp.-
#Pages 6
Date of Issue