| Presentation | 2002/6/20 A study of compact and multi-banks memory suitable for LSI Tomohiro INOUE, Takahiro SASAKI, Tetsuo HIRONAKA, Tetsushi KOIDE, Hans Jurgen MATTAUSCH, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years, instruction issue width have been increased, which requires high memory bandwidth to achive high performance. As the conventional tequnique to realizes high bandwidth memory systems, the multi-ports memory systems with a multi-banks and crossbar memory are proposed. However, these conventional memory systems can not achive high performance within small chip area. In this papar, we propose memory systems with small chip area, using multi-stage interconnection network, and evaluate its circuit size and its bank conflict probability by using a trace driven simulator. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multi Bank Memory / Multi Stage Interconnection Network / On-chip Multiprocessor |
| Paper # | CAS2002-22 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2002/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study of compact and multi-banks memory suitable for LSI |
| Sub Title (in English) | |
| Keyword(1) | Multi Bank Memory |
| Keyword(2) | Multi Stage Interconnection Network |
| Keyword(3) | On-chip Multiprocessor |
| 1st Author's Name | Tomohiro INOUE |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Takahiro SASAKI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Tetsuo HIRONAKA |
| 3rd Author's Affiliation | Faculty of Information Sciences, Department of Computer Engineering, Hiroshima City University |
| 4th Author's Name | Tetsushi KOIDE |
| 4th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 5th Author's Name | Hans Jurgen MATTAUSCH |
| 5th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| Date | 2002/6/20 |
| Paper # | CAS2002-22 |
| Volume (vol) | vol.102 |
| Number (no) | 161 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |