| Presentation | 2004/6/23 Separation by Bonding Si Islands (SBSI) for Adavanced CMOS LSIs : A Study on Selective Etching of SiGe Layers for SBSI Process(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004)) Takashi YAMAZAKI, Shun-ichiro OHMI, Shinya MORITA, Hiroyuki OHRI, Junichi MUROTA, Masao SAKURABA, Hiroo OMI, Tetsushi SAKAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The etching selectivity of SiGe against Si and the surface roughness after selective etching of the SiGe layer were investigated in samples with SiGe/i-Si(non-doped-Si) stacked layers. It was found that the etching of the i-Si layer could be reduced by decreasing the HN0_3 concentration ; thus, the etching selectivity of SiGe against Si improved by decreasing the HN0_3 concentration. The surface roughness also improved as HN0_3 decreased. Furthermore, the thickness of the Si island fabricated by the SBSI process became uniform by decreasing the HN0_3 concentration. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Silicon on insulator (SOI) substrate / patterned SOI / SiGe / selective etching |
| Paper # | ED2004-50,SDM2004-62 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
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| Conference Date | 2004/6/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Separation by Bonding Si Islands (SBSI) for Adavanced CMOS LSIs : A Study on Selective Etching of SiGe Layers for SBSI Process(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004)) |
| Sub Title (in English) | |
| Keyword(1) | Silicon on insulator (SOI) substrate |
| Keyword(2) | patterned SOI |
| Keyword(3) | SiGe |
| Keyword(4) | selective etching |
| 1st Author's Name | Takashi YAMAZAKI |
| 1st Author's Affiliation | Interdisciplinary Graduate School of Science and Enigineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Shun-ichiro OHMI |
| 2nd Author's Affiliation | Interdisciplinary Graduate School of Science and Enigineering, Tokyo Institute of Technology |
| 3rd Author's Name | Shinya MORITA |
| 3rd Author's Affiliation | Interdisciplinary Graduate School of Science and Enigineering, Tokyo Institute of Technology |
| 4th Author's Name | Hiroyuki OHRI |
| 4th Author's Affiliation | Interdisciplinary Graduate School of Science and Enigineering, Tokyo Institute of Technology |
| 5th Author's Name | Junichi MUROTA |
| 5th Author's Affiliation | Research Institute for Electrical Communications, Tohoku University |
| 6th Author's Name | Masao SAKURABA |
| 6th Author's Affiliation | Research Institute for Electrical Communications, Tohoku University |
| 7th Author's Name | Hiroo OMI |
| 7th Author's Affiliation | NTT Basic Research Laboratories, Nippon Telegraph and Telephone Corporation |
| 8th Author's Name | Tetsushi SAKAI |
| 8th Author's Affiliation | Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology |
| Date | 2004/6/23 |
| Paper # | ED2004-50,SDM2004-62 |
| Volume (vol) | vol.104 |
| Number (no) | 152 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |