Presentation 2004/1/12
A High Power SPOT Switch 1C using AlGaN/GaN HFETs
Hidetoshi ISHIDA, Yutaka HIROSE, Atsuhiko KANDA, Tomohiro MURATA, Yoshito IKEDA, Toshinobu MATSUNO, Kaoru INOUE, Yasuhiro UEMOTO, Tsuyoshi TANAKA, Takashi EGAWA, Daisuke UEDA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A high power SPDT switch 1C using AlGaN/GaN HFETs was demonstrated for the first time. The reduction of on-resistance (Ron) and off-capacitance (Cofif) are necessary to realize GaN switch 1C. A novel Si-doping technique was employed to reduce ohmic contact resistance, which leads to reduction of Ron. Al_2O_3 substrates were adopted to reduce Coff. A GaN SPDT switch 1C with single-stage configuration was designed by using a circuit simulator based on the extracted device parameters. The fabricated SPDT switch 1C showed insertion loss of 0.26dB and isolation of 27dB at 1 GHz. An extremely high power handling capability of 43 W was achieved, which is 10 times higher than that of typical GaAs switch ICs. The chip size was reduced to 40% as compared to typical GaAs switch ICs due to the single-stage circuit configuration.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) GaN / FET / switch / loss / isolation / high power / Al_2O_3
Paper # ED2003-201
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Committee ED
Conference Date 2004/1/12(1days)
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Paper Information
Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A High Power SPOT Switch 1C using AlGaN/GaN HFETs
Sub Title (in English)
Keyword(1) GaN
Keyword(2) FET
Keyword(3) switch
Keyword(4) loss
Keyword(5) isolation
Keyword(6) high power
Keyword(7) Al_2O_3
1st Author's Name Hidetoshi ISHIDA
1st Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.()
2nd Author's Name Yutaka HIROSE
2nd Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
3rd Author's Name Atsuhiko KANDA
3rd Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
4th Author's Name Tomohiro MURATA
4th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
5th Author's Name Yoshito IKEDA
5th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
6th Author's Name Toshinobu MATSUNO
6th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
7th Author's Name Kaoru INOUE
7th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
8th Author's Name Yasuhiro UEMOTO
8th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
9th Author's Name Tsuyoshi TANAKA
9th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
10th Author's Name Takashi EGAWA
10th Author's Affiliation Research Center for Micro-Structure Devices, Nagoya Institute of Technology
11th Author's Name Daisuke UEDA
11th Author's Affiliation Semiconductor Research Laboratory, Matsushita Electric Industrial Co., Ltd.
Date 2004/1/12
Paper # ED2003-201
Volume (vol) vol.103
Number (no) 558
Page pp.pp.-
#Pages 5
Date of Issue