| Presentation | 2003/11/11 A 43-Gb/s Low-jitter Output-circuit Design for a 16:1 MUX IC Module Based on SiGe HBT Technology T. Masuda, N. Shiramizu, K. Ohhata, K. Watanabe, T. Harada, H. Kikuchi, K. Washio, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A high-speed low-jitter output-circuit for a 43-Gb/s MUX IC module was designed and tested. To reduce the jitter of the output waveform, the ringing shown in a waveform that leads to the deterministic jitter was analyzed. A methodology to find the optimal degeneration resistance in the output circuit was devised and used to obtain both small jitter and short rise time (Tr) and fall time (Tf). A good output waveform with Tr and Tf of 11 ps and total jitter of 1.3 ps is obtained, and is used to verify the impact of the proposed methodology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MUX / output circuit / jitter / ringing / rise time / fall time |
| Paper # | ED2003-176 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2003/11/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 43-Gb/s Low-jitter Output-circuit Design for a 16:1 MUX IC Module Based on SiGe HBT Technology |
| Sub Title (in English) | |
| Keyword(1) | MUX |
| Keyword(2) | output circuit |
| Keyword(3) | jitter |
| Keyword(4) | ringing |
| Keyword(5) | rise time |
| Keyword(6) | fall time |
| 1st Author's Name | T. Masuda |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | N. Shiramizu |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 3rd Author's Name | K. Ohhata |
| 3rd Author's Affiliation | Renesas Northern Japan Semiconductor, Inc. |
| 4th Author's Name | K. Watanabe |
| 4th Author's Affiliation | Device Development Center, Hitachi, Ltd. |
| 5th Author's Name | T. Harada |
| 5th Author's Affiliation | Device Development Center, Hitachi, Ltd. |
| 6th Author's Name | H. Kikuchi |
| 6th Author's Affiliation | Device Development Center, Hitachi, Ltd. |
| 7th Author's Name | K. Washio |
| 7th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 2003/11/11 |
| Paper # | ED2003-176 |
| Volume (vol) | vol.103 |
| Number (no) | 437 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |