講演名 | 2003/6/23 Effects of Self-Aligned Field Induced Drain with Double Spacer on the Characteristics of Pol-Si TFT (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)) , |
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抄録(和) | |
抄録(英) | The electric characteristics of Field Induced Drain (FID) poly-Si thin film transistors (poly-Si TFT's) with an independently biased self-aligned sub gate using a double space process are investigated. The FID poly-Si TFT reduced the off-state leakage and enlarged the on/off current ratio compared with conventional and LDD (Lightly Doped Drain) TFTs. The self-aligned double spacer process removed the sub gate misalignment error and the length of the sub gate can be easily controlled by poly-Si thickness and hard mask. As the effective sub gate length is increased, the drive current is decreased. However, the optimum sub gate length and voltage are investigated with the on/off state currents and the hot carrier degradation effects. |
キーワード(和) | |
キーワード(英) | Poly-Si Thin-film Transistor (TFT) / Field Induced Drain (FID) / Self-Align / Sub Gate / Double Spacer Process |
資料番号 | ED2003-69,SDM2003-80 |
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研究会情報 | |
研究会 | ED |
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開催期間 | 2003/6/23(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Electron Devices (ED) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | Effects of Self-Aligned Field Induced Drain with Double Spacer on the Characteristics of Pol-Si TFT (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)) |
サブタイトル(和) | |
キーワード(1)(和/英) | / Poly-Si Thin-film Transistor (TFT) |
第 1 著者 氏名(和/英) | / Jeong-Ah Ahn |
第 1 著者 所属(和/英) | Electrical and Computer Engineering Division, Pohang University of Science and Technology |
発表年月日 | 2003/6/23 |
資料番号 | ED2003-69,SDM2003-80 |
巻番号(vol) | vol.103 |
号番号(no) | 159 |
ページ範囲 | pp.- |
ページ数 | 4 |
発行日 |