| Presentation | 2003/2/3 Binary Decision Diagram Logic Integrated Circuit Subsystems Based on Control of Compound Semiconductor Nanowire Networks Seiya KASAI, Miki YUMOTO, Hideki HASEGAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To realize ultra-high density and ultra-low power consumption quantum nanodevice logic integrated circuits, implementation of logic subsystems by a hexagonal quantum BDD logic circuit approach using compound semiconductor-based nanowire networks is investigated. BDD subsystems including adders and comparators are designed based on planar hexagonal layout without nanowire crossovers. Circuit fabrication process realizing 4.5×10^7 devices/cm^2 is developed. QWR-based BDD 2-bit and 4-bit adders are successfully fabricated and correct operation of the 2-bit adder is confirmed in a classical transport regime at room temperature. Design of register circuits utilizing WPG nanodevices is also discussed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Binary decision diagram(BDD) / Quantum nanodevice / Subsystem / Adder / Nanowire network |
| Paper # | ED2002-284 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2003/2/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Binary Decision Diagram Logic Integrated Circuit Subsystems Based on Control of Compound Semiconductor Nanowire Networks |
| Sub Title (in English) | |
| Keyword(1) | Binary decision diagram(BDD) |
| Keyword(2) | Quantum nanodevice |
| Keyword(3) | Subsystem |
| Keyword(4) | Adder |
| Keyword(5) | Nanowire network |
| 1st Author's Name | Seiya KASAI |
| 1st Author's Affiliation | Research Center for Integrated Quantum Electronics and Graduate School of Electronics and Information Engineering, Hokkaido University() |
| 2nd Author's Name | Miki YUMOTO |
| 2nd Author's Affiliation | Research Center for Integrated Quantum Electronics and Graduate School of Electronics and Information Engineering, Hokkaido University |
| 3rd Author's Name | Hideki HASEGAWA |
| 3rd Author's Affiliation | Research Center for Integrated Quantum Electronics and Graduate School of Electronics and Information Engineering, Hokkaido University |
| Date | 2003/2/3 |
| Paper # | ED2002-284 |
| Volume (vol) | vol.102 |
| Number (no) | 638 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |