Presentation 2003/1/10
Self-Bias Low Noise MMIC Amplifier for APAA with Depressed Gain Variation
Koji YAMANAKA, Kazutomi MORI, Hiroshi IKEMATSU, Yoshinbu SASAKI, Masatoshi NAKAYAMA,
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Abstract(in English) In this paper, a Ka-band self-bias Low-Noise MMIC amplifier is presented, which is equipped with a bias circuit that compensates gain variation of self-bias amplifier between chips due to process variations. The Ka-band low noise MMIC amplifier with proposed bias circuit was designed and manufactured. It was proved that the proposed bias circuit reduced the gain variation between chips from 0.8 dB RMS to 0.3 dB RMS. This amplifier is suitable for active phased array applications.
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Keyword(in English) Active Phased Array Antenna / Self-Bias / MMIC / Amplifier / Process Variation
Paper # ED2002-273,MW2002-160
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Committee ED
Conference Date 2003/1/10(1days)
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Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Self-Bias Low Noise MMIC Amplifier for APAA with Depressed Gain Variation
Sub Title (in English)
Keyword(1) Active Phased Array Antenna
Keyword(2) Self-Bias
Keyword(3) MMIC
Keyword(4) Amplifier
Keyword(5) Process Variation
1st Author's Name Koji YAMANAKA
1st Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center()
2nd Author's Name Kazutomi MORI
2nd Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
3rd Author's Name Hiroshi IKEMATSU
3rd Author's Affiliation Mitsubishi Electric Corporation Communication Systems Center
4th Author's Name Yoshinbu SASAKI
4th Author's Affiliation Mitsubishi Electric Corporation High Frequency & Optical Semiconductor Division
5th Author's Name Masatoshi NAKAYAMA
5th Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
Date 2003/1/10
Paper # ED2002-273,MW2002-160
Volume (vol) vol.102
Number (no) 557
Page pp.pp.-
#Pages 4
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