Presentation 2003/1/9
1.7-W 50-Gbit/s InP HEMT 4:1 Multiplexer IC with a Multi-phase Clock Architecture
Kimikazu Sano, Koichi Murata, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki,
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Abstract(in English) Low-power and high-speed operation of a 4:1 multiplexer IC with a multi-phase clock architecture is reported. The architecture features a toggle-type flip-flop (TFF) that generates a four-phase clock, and a series-gated 4:1 selector (SEL). The fabricated IC using InP HEMTs operates at 50 Gbit/s error-free with 1.71-W power consumption and 1-Vpp output amplitude. The power consumption is less than 1/3 that of a conventional tree-type InP HEMT 4:1 multiplexer IC and is achieved without any reduction of operation speed and output amplitude.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) 4:1Multiplexer / Multi-phase clock / InP HEMT / 40-Gbit / s optical communication systems
Paper # ED2002-259,MW2002-146
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Committee ED
Conference Date 2003/1/9(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 1.7-W 50-Gbit/s InP HEMT 4:1 Multiplexer IC with a Multi-phase Clock Architecture
Sub Title (in English)
Keyword(1) 4:1Multiplexer
Keyword(2) Multi-phase clock
Keyword(3) InP HEMT
Keyword(4) 40-Gbit
Keyword(5) s optical communication systems
1st Author's Name Kimikazu Sano
1st Author's Affiliation NTT Photonics Laboratories()
2nd Author's Name Koichi Murata
2nd Author's Affiliation NTT Photonics Laboratories
3rd Author's Name Suehiro Sugitani
3rd Author's Affiliation NTT Photonics Laboratories
4th Author's Name Hirohiko Sugahara
4th Author's Affiliation NTT Photonics Laboratories
5th Author's Name Takatomo Enoki
5th Author's Affiliation NTT Photonics Laboratories
Date 2003/1/9
Paper # ED2002-259,MW2002-146
Volume (vol) vol.102
Number (no) 556
Page pp.pp.-
#Pages 6
Date of Issue