| Presentation | 2004/1/29 Development of a mA-Order Iddq Test Method and Application to Real Devices Yasuyuki NOZUYAMA, Mahito SHIDO, Yoshitomo NAKANISHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the progress of process for fabricating system LSIs, failures hardly detected by logic-level tests have increased and Iddq test has become important. Its effectiveness, however, has been degraded since most of fault-free DSM devices have one or several mA of Iddq which obstructs effective detection of Iddq anomaly. We have developed a mA-order Iddq test method with practical sensitivity for detecting abnormal Iddq from lOOmicroA (@1mA Iddq) to ISOmicroA (@3mA Iddq) and reliable Pass/Fail judgment under process variations, by grouping strobe points and fitting Iddq data based on the evaluation of process margin samples and selecting an method to avoid misjudgments. We have applied the Iddq test method to real devices and confirmed its effectiveness. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Iddq test / mA order Iddq / process margin samples / strobe point grouping / stuck-at fault / bridge fault |
| Paper # | CPM2003-170,ICD2003-209 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2004/1/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of a mA-Order Iddq Test Method and Application to Real Devices |
| Sub Title (in English) | |
| Keyword(1) | Iddq test |
| Keyword(2) | mA order Iddq |
| Keyword(3) | process margin samples |
| Keyword(4) | strobe point grouping |
| Keyword(5) | stuck-at fault |
| Keyword(6) | bridge fault |
| 1st Author's Name | Yasuyuki NOZUYAMA |
| 1st Author's Affiliation | Test Engineering Gr., System LSI Design Dept., System LSI Div., Semiconductor Company, Toshiba Corporation() |
| 2nd Author's Name | Mahito SHIDO |
| 2nd Author's Affiliation | Test Engineering Gr., System LSI Design Dept., System LSI Div., Semiconductor Company, Toshiba Corporation |
| 3rd Author's Name | Yoshitomo NAKANISHI |
| 3rd Author's Affiliation | CAT Engineering Gr., Test System Development Dept., Toshiba Microelectronics Corporation |
| Date | 2004/1/29 |
| Paper # | CPM2003-170,ICD2003-209 |
| Volume (vol) | vol.103 |
| Number (no) | 645 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |