Presentation 2004/1/29
Back Side Failure Analysis Technique for Multiple Interconnects
T. Nakashima, A. Onoyama, E. Yoshida, T. Koyama, J. Komori, Y. Mashiko,
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Abstract(in English) We developed a new fault isolation technique for multiple interconnect structure in SOC devices, which applies the voltage contrast method from the rear side of the exposed metal interconnects. It makes possible to detect failure points in lower layers which it is difficult to be detected by conventional techniques. Also the technique realizes the efficient analysis, as it is possible to observe every exposed node of circuit.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Multiple Interconnects / Back side / Voltage contrast
Paper # CPM2003-162,ICD2003-201
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Conference Information
Committee CPM
Conference Date 2004/1/29(1days)
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Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Back Side Failure Analysis Technique for Multiple Interconnects
Sub Title (in English)
Keyword(1) Multiple Interconnects
Keyword(2) Back side
Keyword(3) Voltage contrast
1st Author's Name T. Nakashima
1st Author's Affiliation Renesas Semiconductor Engineering Corporation()
2nd Author's Name A. Onoyama
2nd Author's Affiliation Mitsubishi Electric Corporation
3rd Author's Name E. Yoshida
3rd Author's Affiliation Renesas Technology Corporation
4th Author's Name T. Koyama
4th Author's Affiliation Renesas Technology Corporation
5th Author's Name J. Komori
5th Author's Affiliation Renesas Technology Corporation
6th Author's Name Y. Mashiko
6th Author's Affiliation Renesas Technology Corporation
Date 2004/1/29
Paper # CPM2003-162,ICD2003-201
Volume (vol) vol.103
Number (no) 645
Page pp.pp.-
#Pages 5
Date of Issue