| Presentation | 2003/1/23 DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs K. Kushida, O. Hirabayashi, A. Suzuki, T. Yabe, A. Kawasumi, Y. Takeyama, A. Tohata, N. Otsuka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Design-For-Test (DFT) techniques for acquiring fail bit map of at-speed function with conventional wafer test equipment are proposed. SRAM core is operated with high-frequency clock generated by gain-suppressed VCO which can reduce clock jitter. The data are outputted with data out strobe control circuit synchronizing with external low-frequency clock. Using these techniques, the SRAM chip appears to be operated with low-frequency tester clock while SRAM core is operated with high-frequency internal clock. Therefore, fail bit map of high-frequency operation can be obtained with conventional wafer test equipment. The at-speed test with fail bit map acquisition allows slow bit cell replacement to spare cell or chip-by-chip internal timing optimization with fuse-blowing. It results in a drastic reduction in test cost and performance yield improvement. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SRAM / DFT / VCO / BIST / At-specd test |
| Paper # | CPM2002-140 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2003/1/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | DFT |
| Keyword(3) | VCO |
| Keyword(4) | BIST |
| Keyword(5) | At-specd test |
| 1st Author's Name | K. Kushida |
| 1st Author's Affiliation | Semiconductor Company,Toshiba Corporation() |
| 2nd Author's Name | O. Hirabayashi |
| 2nd Author's Affiliation | Semiconductor Company,Toshiba Corporation |
| 3rd Author's Name | A. Suzuki |
| 3rd Author's Affiliation | Semiconductor Company,Toshiba Corporation |
| 4th Author's Name | T. Yabe |
| 4th Author's Affiliation | Semiconductor Company,Toshiba Corporation |
| 5th Author's Name | A. Kawasumi |
| 5th Author's Affiliation | Semiconductor Company,Toshiba Corporation |
| 6th Author's Name | Y. Takeyama |
| 6th Author's Affiliation | Semiconductor Company,Toshiba Corporation |
| 7th Author's Name | A. Tohata |
| 7th Author's Affiliation | Toshiba Microelectronics Corporation |
| 8th Author's Name | N. Otsuka |
| 8th Author's Affiliation | Semiconductor Company,Toshiba Corporation |
| Date | 2003/1/23 |
| Paper # | CPM2002-140 |
| Volume (vol) | vol.102 |
| Number (no) | 620 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |