Presentation 2003/7/11
Design of a Network Switch using Asynchronous SFQ Logic Gates
Yoshihiro WAKIMIZU, Yideyuki YAMASAKI, Hiroaki MYOREN, Susumu TAKADA,
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Abstract(in English) In this study, we designed a 4×4 Banyan switch using the asynchronous single flux quantum (SFQ) logic gates. An address comparator for Batcher sorter and a contention detection circuit were composed using asynchronous SFQ gates. By using the asynchronous system for the circuit, no clock SFQ pulses are required. It is expected that short propagation delay and small circuit scale since there is no waiting time for clock pulses and Josephson transmission lines and D-FF gates for the synchronous system. On the assumption of the Nb/Al-AlO_x/Nb Josephson junction of J_c=1kA/cm^2, correct operation of 10GHz were confirmed by JSPICE3. The operations at 20GHz and 40GHz were confirmed by assuming of J_c=4kA/cm^2.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Asynchronous SFQ System / Banyan Switch / Address comparator / Contention detection circuits
Paper # SCE2003-14
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Committee SCE
Conference Date 2003/7/11(1days)
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Paper Information
Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of a Network Switch using Asynchronous SFQ Logic Gates
Sub Title (in English)
Keyword(1) Asynchronous SFQ System
Keyword(2) Banyan Switch
Keyword(3) Address comparator
Keyword(4) Contention detection circuits
1st Author's Name Yoshihiro WAKIMIZU
1st Author's Affiliation Faculty of Engineering, Saitama University()
2nd Author's Name Yideyuki YAMASAKI
2nd Author's Affiliation Faculty of Engineering, Saitama University
3rd Author's Name Hiroaki MYOREN
3rd Author's Affiliation Faculty of Engineering, Saitama University
4th Author's Name Susumu TAKADA
4th Author's Affiliation Faculty of Engineering, Saitama University
Date 2003/7/11
Paper # SCE2003-14
Volume (vol) vol.103
Number (no) 211
Page pp.pp.-
#Pages 4
Date of Issue