| Presentation | 2004/6/11 A Design for 2-pattern Testability of System-on-Chip Interconnects Yuusuke SAGA, Tomokazu YONEDA, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Testing faults on interconnects of system-on-chip (SoC) has become more important because of high integration of semiconductors. The faults can be tested by 2-pattern testing. 2-pattern testing means application of consecutive two patterns and observation of one test sequence. In this paper, we present two DFT methods for 2-pattern testability of interconnect. One DFT method utilizes EXTEST mode of IEEE P1500 wrappers and support testing through serial TAM. Other doesn't use IEEE P1500 wrappers, and utilizes existing interconnects as much as possible. In a case study, we show advantages that hardware overhead of proposed method is lower than that of the DFT method based on consecutive testability. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | system-on-chip / interconnect / design for testability / crosstalk-induced faults / 2-pattern testability / test access mechanism |
| Paper # | DC2004-10 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2004/6/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design for 2-pattern Testability of System-on-Chip Interconnects |
| Sub Title (in English) | |
| Keyword(1) | system-on-chip |
| Keyword(2) | interconnect |
| Keyword(3) | design for testability |
| Keyword(4) | crosstalk-induced faults |
| Keyword(5) | 2-pattern testability |
| Keyword(6) | test access mechanism |
| 1st Author's Name | Yuusuke SAGA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City() |
| 2nd Author's Name | Tomokazu YONEDA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City |
| Date | 2004/6/11 |
| Paper # | DC2004-10 |
| Volume (vol) | vol.104 |
| Number (no) | 130 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |