Presentation	2004/6/11 Relationship between Fault Coverage and Defect Level in Consideration of BIST Faults Yoshiyuki NAKAMURA, Hideo FUJIWARA,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	There are some well-known equations which derive the defect level from fault coverage. However, these equations are only true under the assumption that the test equipment is fault-free. Therefore to apply these equations, the test equipment requires exhaustive testing to make sure it is fault-free. As BIST is a part of the test equipment, we have to exhaustively test it in every chip that greatly increases the cost of testing. In this paper, we introduce a new method to derive defect level from fault coverage without assuming the test equipment as fault-free. Our method does not require exhaustive test for BIST thus reduce the cost of testing.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	BIST / Fault coverage / Defect level
Paper #	DC2004-9
Date of Issue

Conference Information
Committee	DC
Conference Date	2004/6/11(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Relationship between Fault Coverage and Defect Level in Consideration of BIST Faults
Sub Title (in English)
Keyword(1)	BIST
Keyword(2)	Fault coverage
Keyword(3)	Defect level
1st Author's Name	Yoshiyuki NAKAMURA
1st Author's Affiliation	Nara Institute of Science and Technology (NAIST):NEC Electronics Corporation()
2nd Author's Name	Hideo FUJIWARA
2nd Author's Affiliation	Nara Institute of Science and Technology (NAIST)
Date	2004/6/11
Paper #	DC2004-9
Volume (vol)	vol.104
Number (no)	130
Page	pp.pp.-
#Pages	6
Date of Issue