Presentation 2003/11/21
A Logical Synthesis Methodology for Two-phase and Differential Logic Technology ASDDL ASD-CMOS
Yoshinori TANAKA, Masao MORIMOTO, Makoto NAGATA, Kazuo TAKI,
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Abstract(in English) We propose a logical synthesis methodology for a high speed logic technology ASDDL/ASD-CMOS, which are two-phase and differential logic circuit. Because of its originality, it was unable to synthesize a AS-DDL/ASD-CMOS circuit as yet. But we have been able to synthesize a its circuit by proposing a original cell library and transforming tool to apply a logical synthesis environment for CMOS circuit to ASDDL/ASD-CMOS circuit. The delay time of synthesized ASDDL circuit was 126% of full customed.
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Keyword(in English) two-phase and differential logic circuit / ASDDL / ASD-CMOS / logical synthesis
Paper # DC2003-43
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Conference Date 2003/11/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Logical Synthesis Methodology for Two-phase and Differential Logic Technology ASDDL ASD-CMOS
Sub Title (in English)
Keyword(1) two-phase and differential logic circuit
Keyword(2) ASDDL
Keyword(3) ASD-CMOS
Keyword(4) logical synthesis
1st Author's Name Yoshinori TANAKA
1st Author's Affiliation Graduate School of Science and Technology, Kobe University()
2nd Author's Name Masao MORIMOTO
2nd Author's Affiliation Graduate School of Science and Technology, Kobe University
3rd Author's Name Makoto NAGATA
3rd Author's Affiliation Department of Computer and Systems Engineering, Kobe University
4th Author's Name Kazuo TAKI
4th Author's Affiliation AIL Co.,Ltd.
Date 2003/11/21
Paper # DC2003-43
Volume (vol) vol.103
Number (no) 480
Page pp.pp.-
#Pages 6
Date of Issue