| Presentation | 2003/11/21 On the Acceleration of Asynchronous Circuit Synthesis TOmohiro YONEDA, Chris MYERS, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a decomposition-based logic synthesis method for speed-independent circuit design such that each output is synthesized individually. Since the cost of logic synthesis increases rapidly as the specification becomes larger, this approach that keeps the specification small by decomposition can potentially be applied to synthesize circuits for which the conventional methods cannot be successfully applied. The proposed method begins by reducing the specification to include only the output of interest and its trigger signals. Next, if the synthesis process fails due to the lack of sufficient input signals, the reachable state space for this reduced specification is analyzed to determine a minimal number of additional input signals. This paper presents the details of this input decision algorithm, and also shows some experimental results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Decomposition / Logic Synthesis / Speed-Independent Circuits / STG |
| Paper # | DC2003-42 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2003/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the Acceleration of Asynchronous Circuit Synthesis |
| Sub Title (in English) | |
| Keyword(1) | Decomposition |
| Keyword(2) | Logic Synthesis |
| Keyword(3) | Speed-Independent Circuits |
| Keyword(4) | STG |
| 1st Author's Name | TOmohiro YONEDA |
| 1st Author's Affiliation | Infrastructure Systems Research Division, National Institute of Informatics() |
| 2nd Author's Name | Chris MYERS |
| 2nd Author's Affiliation | ChrisMYERS†Electrical and Computer Engineering, University of Utah |
| Date | 2003/11/21 |
| Paper # | DC2003-42 |
| Volume (vol) | vol.103 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
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