Presentation 2003/11/21
A Method of Design for Delay Fault Testability of Controllers
Tsuyoshi IWAGAKI, Satoshi OHTAKE, Hideo FUJIWARA,
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Abstract(in English) This paper proposes a non-scan testing scheme to enhance delay fault testability of controllers. In this scheme, the original behavior of a given controller is used in test application, and the faults that cannot be detected by the original behavior are tested by an extra logic called an invalid test state/transition generator (ISTG) . Our scheme allows the following: achieving (1) short test generation time, (2) short test application time and (3) at-speed testing. We experimentally show the effectiveness of our method. In our method, ISTGs can be designed flexibly in response to the test qualities demanded by circuit designers.
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Keyword(in English) Controller / Delay fault / Design for testability / Invalid test state/transition generator / At-speed test / Non-scan design
Paper # DC2003-38
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Conference Date 2003/11/21(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Method of Design for Delay Fault Testability of Controllers
Sub Title (in English)
Keyword(1) Controller
Keyword(2) Delay fault
Keyword(3) Design for testability
Keyword(4) Invalid test state/transition generator
Keyword(5) At-speed test
Keyword(6) Non-scan design
1st Author's Name Tsuyoshi IWAGAKI
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology()
2nd Author's Name Satoshi OHTAKE
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
3rd Author's Name Hideo FUJIWARA
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
Date 2003/11/21
Paper # DC2003-38
Volume (vol) vol.103
Number (no) 480
Page pp.pp.-
#Pages 6
Date of Issue