Presentation 2003/11/21
An Improvement of the Test Plan Generation Algorithm for Strongly Testable Datapaths
Naoki OKAMOTO, Hideyuki ICHIHARA, Tomoo INOUE, Toshinori HOSOKAWA, Hideo FUJIWARA,
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Abstract(in English) Hierarchical test generation [2] is an efficient method of test generation for VLSI circuits. In this work, we study an improvement of the DFT method [3] based on strong testability of Register-Transfer level (RTL) datapaths. We focus on the algorithm, which is a part of the DFT/test plan generation algorithm [3], for generating a controlling forest in a given RTL datapath, we propose a heuristic algorithm for finding a controlling forest without time conflict. As a result, it can reduce the number of registers with hold operation. Furthermore, we show that our proposed algorithm can be applied to datapaths that do not satisfy the constraint for the previous method [3] , by expressing the information about input registers of a module as a measure of time conflict. Experimental results show that the proposed algorithm is effective in reducing additional hold functions(or hardware overhead), as well as test application time.
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Keyword(in English) Hierarchical test generation / strong testability / datapath / test plan
Paper # DC2003-36
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Conference Date 2003/11/21(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Improvement of the Test Plan Generation Algorithm for Strongly Testable Datapaths
Sub Title (in English)
Keyword(1) Hierarchical test generation
Keyword(2) strong testability
Keyword(3) datapath
Keyword(4) test plan
1st Author's Name Naoki OKAMOTO
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Hideyuki ICHIHARA
2nd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
3rd Author's Name Tomoo INOUE
3rd Author's Affiliation Faculty of Information Sciences, Hiroshima City University
4th Author's Name Toshinori HOSOKAWA
4th Author's Affiliation College of Industrial Technology, Nihon University
5th Author's Name Hideo FUJIWARA
5th Author's Affiliation Graduate School of Info. Science, Nara Institute of Science and Technology
Date 2003/11/21
Paper # DC2003-36
Volume (vol) vol.103
Number (no) 480
Page pp.pp.-
#Pages 6
Date of Issue