Presentation	2003/11/21 Fault Mode Analysis for Single Electron Logic Circuits Toshiaki OHMAMEUDA,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Faults of logic circuits using single electron tunneling transistors (SET) is researched. The circuit simulations using Monte Carlo method show the following results. When a capacitance used in SET is too small, the logic value of the circuit output is fixed to one value. This is as same as the stuck-at faults assumed in the CMOS logic circuits. When a capacitance used in SET is too large, the logic value of the circuit output is unstable for one input value. This fault does not occur in the CMOS logic circuits. Therefore the new fault model is necessary for the single electron circuits.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Single Electron Tunneling Transistor / Single Electron Logic Circuit / Monte Carlo Method / Fault Analysis / Logical Fault / Fault Model
Paper #	DC2003-35
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Conference Information
Committee	DC
Conference Date	2003/11/21(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Fault Mode Analysis for Single Electron Logic Circuits
Sub Title (in English)
Keyword(1)	Single Electron Tunneling Transistor
Keyword(2)	Single Electron Logic Circuit
Keyword(3)	Monte Carlo Method
Keyword(4)	Fault Analysis
Keyword(5)	Logical Fault
Keyword(6)	Fault Model
1st Author's Name	Toshiaki OHMAMEUDA
1st Author's Affiliation	Gunma National College of Technology()
Date	2003/11/21
Paper #	DC2003-35
Volume (vol)	vol.103
Number (no)	480
Page	pp.pp.-
#Pages	5
Date of Issue