| Presentation | 2003/11/21 Test Generation for Sequential Circuits by Logic Simulation using State Partitioning Hirokazu SANO, Hiroyuki YOTSUYANAGI, Masaki HASHIZUME, Takeomi TAMESADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a test generation method for sequential circuits by logic simulation using state partitioning. The test pattern generation method utilized in this work selects the test vector which can bring the state of the circuit into a state that can not be reached by the previous vectors. Two state partition methods are proposed: One is the partition method based on the controllability of flip-flops. The other is the partition method based on the relation between undetected faults and flip-flops. To obtain test vectors that bring the circuit into the states required for detecting undetected faults, the new method partitions flip-flops in a circuit by considering whether the flip-flop is in the subcircuits required for fault excitation or in the subcircuits required for fault propagation. The experimental results show the effectiveness of the state partitioning methods. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | state partitioning / logic simulation / test generate / sequential circuit |
| Paper # | DC2003-34 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2003/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Generation for Sequential Circuits by Logic Simulation using State Partitioning |
| Sub Title (in English) | |
| Keyword(1) | state partitioning |
| Keyword(2) | logic simulation |
| Keyword(3) | test generate |
| Keyword(4) | sequential circuit |
| 1st Author's Name | Hirokazu SANO |
| 1st Author's Affiliation | Faculty of Engineering, Univ. of Tokushima() |
| 2nd Author's Name | Hiroyuki YOTSUYANAGI |
| 2nd Author's Affiliation | Faculty of Engineering, Univ. of Tokushima |
| 3rd Author's Name | Masaki HASHIZUME |
| 3rd Author's Affiliation | Faculty of Engineering, Univ. of Tokushima |
| 4th Author's Name | Takeomi TAMESADA |
| 4th Author's Affiliation | Faculty of Engineering, Univ. of Tokushima |
| Date | 2003/11/21 |
| Paper # | DC2003-34 |
| Volume (vol) | vol.103 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |