Presentation 2003/4/11
High-Level Synthesis of Asynchronous Circuits
Tomohiro YONEDA, Masaki TAKAZONO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) This work proposes an efficient methodology to synthesize timed circuits from high level specification languages. In particular, this paper presents a systematic procedure for translating channel-level models to Petri net descriptions. Care is taken in this translation to guarantee that there are no state coding violations in the resulting nets greatly simplifying the synthesis process. This paper also presents a modular decomposition method to break up the circuit to be synthesized such that an efficient partial order based synthesis approach can be applied to rapidly produce a circuit implementation. This new synthesis technique is demonstrated by its application to the line fetch module from the TITAC2 instruction cache system.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) High level synthesis / timed circuits / Modular synthesis / Partial order reduction / Petri nets / Balsa
Paper # CPSY2003-2,DC2003-2
Date of Issue

Conference Information
Committee DC
Conference Date 2003/4/11(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Vice Chair

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High-Level Synthesis of Asynchronous Circuits
Sub Title (in English)
Keyword(1) High level synthesis
Keyword(2) timed circuits
Keyword(3) Modular synthesis
Keyword(4) Partial order reduction
Keyword(5) Petri nets
Keyword(6) Balsa
1st Author's Name Tomohiro YONEDA
1st Author's Affiliation Infrastructure Systems Research Division, National Institute of Informatics()
2nd Author's Name Masaki TAKAZONO
2nd Author's Affiliation Graduate School of Information Science and Engineering, Tokyo Institute of Technology
Date 2003/4/11
Paper # CPSY2003-2,DC2003-2
Volume (vol) vol.103
Number (no) 19
Page pp.pp.-
#Pages 6
Date of Issue