Presentation 2003/4/11
New Architecture for high performance processor that enables easy addition of functions : PACCS(Packed Code Computing System)
Yukihiko YAMASHITA, Makoto MITSUBAYASHI,
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Abstract(in English) We propose a new architecture called the PACCS (PAcked Code Computing System) for a high performance processor that enable easy addition of functions. Although many configurable processors were proposed, the performance of their basic system is not high. The PACCS architecture can solve this problem. It has high independence between functional units in the processor and the simple interface between a system and a functional units that enables to add functions to a high performance processor easily. It has freedom for the number of operands and the length of immediate data, while the record length of an LI instruction cache memory is fixed. We show that it has sufficient performance with an experimental result of the pioposed processor PACCS-3.
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Keyword(in English) processor architecture / configurable processor / reconfigurable processor / register renaming
Paper # CPSY2003-1,DC2003-1
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Conference Date 2003/4/11(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) New Architecture for high performance processor that enables easy addition of functions : PACCS(Packed Code Computing System)
Sub Title (in English)
Keyword(1) processor architecture
Keyword(2) configurable processor
Keyword(3) reconfigurable processor
Keyword(4) register renaming
1st Author's Name Yukihiko YAMASHITA
1st Author's Affiliation Graduate School of Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name Makoto MITSUBAYASHI
2nd Author's Affiliation Faculty of Engineering, Tokyo Institute of Technology
Date 2003/4/11
Paper # CPSY2003-1,DC2003-1
Volume (vol) vol.103
Number (no) 19
Page pp.pp.-
#Pages 6
Date of Issue