| Presentation | 2003/6/13 Wormhole方式を基にしたバックトラック可能な耐故障スイッチング(ディペンダブルソフトウェアとネットワーク) Manabu SUEISHI, Masato KITAKAMI, Hideo ITO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Parallel computers are now popularly applied to applications where many calculations are required. In a NORA parallel computer, many processors are connected to each other by communication links and calculation results are obtained by communications between processors. It is said that the NORA computer is suitable for massive parallel computers. Since parallel computers include many processors, the failure rate of the parallel computers are higher than that of single-processor computers. From this, many fault-tolerant switching methods, which enable communications between fault-free processors even if faulty processors are included in the parallel computers, have been proposed. The existing methods have problems, however, such as low communication throughput, low fault-tolerant capability, and large hardware overhead. This paper proposes fault-tolerant switching by improving Wormhole switching, which is raid to achieve high throughput. The proposed switching inserts dummy flits after the header flit. By overwriting the header flit to the dummy flit, backtrack is implemented without hardware overhead. Computer simulations say that in a 16 by 16 2D torus, for example, the throughput of proposed method is almost equal to that of existing methods which require large hardware overhead if the number of the faulty nodes is less then 40. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NORA parallel computer / switching / Wormhole switching / fault-tolerance / Dummy Flit / Backtrack |
| Paper # | DC2003-6 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2003/6/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | NORA parallel computer |
| Keyword(2) | switching |
| Keyword(3) | Wormhole switching |
| Keyword(4) | fault-tolerance |
| Keyword(5) | Dummy Flit |
| Keyword(6) | Backtrack |
| 1st Author's Name | Manabu SUEISHI |
| 1st Author's Affiliation | Graduate School of Science and Technology, Chiba University() |
| 2nd Author's Name | Masato KITAKAMI |
| 2nd Author's Affiliation | Faculty of Engineering, Chiba University |
| 3rd Author's Name | Hideo ITO |
| 3rd Author's Affiliation | Faculty of Engineering, Chiba University |
| Date | 2003/6/13 |
| Paper # | DC2003-6 |
| Volume (vol) | vol.103 |
| Number (no) | 134 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |