| Presentation | 2003/2/14 Estimation of Fault Coverage in Path Delay Fault Testing Masayasu Fukunaga, Koji Ishida, Seiji Kajihara, Sadami Takeoka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a method to estimate fault coverage for path delay faults. There exist problems in path delay testing that the number of paths of a logic circuit may increase exponentially to the number of gates and there sometimes exist many untestable paths. As fault coverage would be very low, we should calculate fault efficiency by computing all testable paths but it is difficult to calculate the exact number of testable paths. The method proposed in this paper extracts a part of potentially testable paths and estimates fault efficiency of test patterns based on the rate of the number of testable paths. Finally, from experimental results, we show the effectiveness of the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | path delay fault / untestable path / potentially testable path / fault coverage / fault efficiency |
| Paper # | DC2002-85 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2003/2/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Estimation of Fault Coverage in Path Delay Fault Testing |
| Sub Title (in English) | |
| Keyword(1) | path delay fault |
| Keyword(2) | untestable path |
| Keyword(3) | potentially testable path |
| Keyword(4) | fault coverage |
| Keyword(5) | fault efficiency |
| 1st Author's Name | Masayasu Fukunaga |
| 1st Author's Affiliation | Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology() |
| 2nd Author's Name | Koji Ishida |
| 2nd Author's Affiliation | Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology |
| 3rd Author's Name | Seiji Kajihara |
| 3rd Author's Affiliation | Graduate School of Computer Science and System Engineering, Kyushu Institute of Technology:Center for Microelectronics Systems, Kyushu Institute of Technology |
| 4th Author's Name | Sadami Takeoka |
| 4th Author's Affiliation | Matsushita Electric Industrial Co., Ltd. Semiconductor Company |
| Date | 2003/2/14 |
| Paper # | DC2002-85 |
| Volume (vol) | vol.102 |
| Number (no) | 658 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |