| Presentation | 2003/2/14 A DFT method for RTL data paths based on strong testability to reduce test application time Shintaro NAGAI, Satoshi OHTAKE, Hideo FUJIWARA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a non-scan DFT method based on strong testability of register-transfer level data paths to reduce test application time. The proposed test generation method for data paths is based on hierarchical test generation. In the test generation method, test vectors and a test plan are generated for each combinational hardware element of a data path. The method generates test vectors only once for combinational hardware elements consisted of the same logic circuit. These hardware elements can be tested by using the same test vectors. To reduce test application time, we test those hardware elements concurrently. We also consider testing combinational hardware elements in a pipelined fasion. The method can achieve complete fault efficiency and allows at-speed testing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | design for testability / register-transfer level / hierarchical test generation / concurrent test / pipeline test / complete fault efficiency |
| Paper # | DC2002-84 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2003/2/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DFT method for RTL data paths based on strong testability to reduce test application time |
| Sub Title (in English) | |
| Keyword(1) | design for testability |
| Keyword(2) | register-transfer level |
| Keyword(3) | hierarchical test generation |
| Keyword(4) | concurrent test |
| Keyword(5) | pipeline test |
| Keyword(6) | complete fault efficiency |
| 1st Author's Name | Shintaro NAGAI |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2003/2/14 |
| Paper # | DC2002-84 |
| Volume (vol) | vol.102 |
| Number (no) | 658 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |