Presentation | 2003/2/14 Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits Denduang PRADUBSUWUN, Tomohiro YONEDA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper proposes a timed trace theoretic verification algorithm with partial order reduction technique so that both the safety failures and timing failures of timed circuits can be efficiently detected. This algorithm follows the framework of the timed trace theoretic verification that is constructed in accordance with the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Timed trace theory / timed circuits / formal verification / safety / timing failures |
Paper # | DC2002-83 |
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Committee | DC |
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Conference Date | 2003/2/14(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits |
Sub Title (in English) | |
Keyword(1) | Timed trace theory |
Keyword(2) | timed circuits |
Keyword(3) | formal verification |
Keyword(4) | safety |
Keyword(5) | timing failures |
1st Author's Name | Denduang PRADUBSUWUN |
1st Author's Affiliation | Graduate School of Information Science and Engineering,T okyo Institute of Technology() |
2nd Author's Name | Tomohiro YONEDA |
2nd Author's Affiliation | Infrastructure Systems Research Division, National Institute of Informatics |
Date | 2003/2/14 |
Paper # | DC2002-83 |
Volume (vol) | vol.102 |
Number (no) | 658 |
Page | pp.pp.- |
#Pages | 6 |
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