Presentation | 2003/2/14 Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability Tetsuo UCHIYAMA, Tomokazu YONEDA, Hideo FUJIWARA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Test access mechanism and test scheduling are integral parts of SoC test. This paper introduces a concept of testability called consecutive testability and presents a design-for-testability method for making an SoC consecutively testable. The proposed DFT method creates TAM design and test schedule by using integer linear programming, and makes a given SoC consecutively testable by co-optimizing area overhead and test application time. For consecutive testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from the SoC inputs consecutively at speed of system clock. Similarly the test responses are propagated to the SoC outputs from the core outputs consecutively at speed of system clock. Therefore, the method can test not only logic faults such as stuck-at faults, but also timing faults such as delay faults that require consecutive application of test patterns at speed of system clock. The proposed DFT method introduces low area overhead because existing interconnects are used as a part of TAM. Experimintal results show advantages of the proposed method compared to test bus architecture which is a well known TAM design. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | system-on-a-chip / design for testability / test access mechanism / test scheduling / consecutive testability / Co-optimization |
Paper # | DC2002-82 |
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Committee | DC |
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Conference Date | 2003/2/14(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability |
Sub Title (in English) | |
Keyword(1) | system-on-a-chip |
Keyword(2) | design for testability |
Keyword(3) | test access mechanism |
Keyword(4) | test scheduling |
Keyword(5) | consecutive testability |
Keyword(6) | Co-optimization |
1st Author's Name | Tetsuo UCHIYAMA |
1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
2nd Author's Name | Tomokazu YONEDA |
2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
3rd Author's Name | Hideo FUJIWARA |
3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
Date | 2003/2/14 |
Paper # | DC2002-82 |
Volume (vol) | vol.102 |
Number (no) | 658 |
Page | pp.pp.- |
#Pages | 6 |
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