Presentation 2003/2/14
Analysis Method of Analog Circuits by an Operation-Region Model
Daisuke KATO, Yukiya MIURA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) MOS transistors have three operation regions, cut-off, linear and saturation regions. An operation-region model is a modeling method, which is based on observation of change in operation regions of MOS transistors. We can analyze analog circuits, digital circuits and mixed-signal circuits by the operation-region model because it does not depend on structures of circuits. In this paper, we discuss analysis and testing of analog circuits by the operation-region model. First, we propose an analysis method of analog circuits by the operation-region model, and we apply it for analyzing ITC benchmark circuits. Next, we also propose a method for applying the operation-region model to testing. Finally, we propose and verify a more efficient method for analyzing analog circuits by the operation-region model.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Circuit Model / Analog Circuits / Analysis and Testing / CMOS Circuits / Operation Regions
Paper # DC2002-81
Date of Issue

Conference Information
Committee DC
Conference Date 2003/2/14(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis Method of Analog Circuits by an Operation-Region Model
Sub Title (in English)
Keyword(1) Circuit Model
Keyword(2) Analog Circuits
Keyword(3) Analysis and Testing
Keyword(4) CMOS Circuits
Keyword(5) Operation Regions
1st Author's Name Daisuke KATO
1st Author's Affiliation The Graduate School of Engineering, Tokyo Metropolitan University()
2nd Author's Name Yukiya MIURA
2nd Author's Affiliation The Graduate School of Engineering, Tokyo Metropolitan University
Date 2003/2/14
Paper # DC2002-81
Volume (vol) vol.102
Number (no) 658
Page pp.pp.-
#Pages 6
Date of Issue