Presentation	2003/2/14 Study on the Relation between Test Escape and Total Fault Coverage Hiroki WADA, Michinobu NAKAO, Tadasu OTSUBO, Makoto OTANI, Kazumi HATAYAMA, Yoshio TAKAMINE,
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Abstract(in English)	The method to estimate the fault coverage achieving the required test escape rate of the LSI under designing based on the results of other LSIs' final tests is presented.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Test Escape / Fault Coverage / Fault Model
Paper #	DC2002-79
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Committee	DC
Conference Date	2003/2/14(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Study on the Relation between Test Escape and Total Fault Coverage
Sub Title (in English)
Keyword(1)	Test Escape
Keyword(2)	Fault Coverage
Keyword(3)	Fault Model
1st Author's Name	Hiroki WADA
1st Author's Affiliation	Semiconductor & Integrated Circuits Group, Hitachi Ltd.()
2nd Author's Name	Michinobu NAKAO
2nd Author's Affiliation	Semiconductor & Integrated Circuits Group, Hitachi Ltd.
3rd Author's Name	Tadasu OTSUBO
3rd Author's Affiliation	Semiconductor & Integrated Circuits Group, Hitachi Ltd.
4th Author's Name	Makoto OTANI
4th Author's Affiliation	Semiconductor & Integrated Circuits Group, Hitachi Ltd.
5th Author's Name	Kazumi HATAYAMA
5th Author's Affiliation	Semiconductor & Integrated Circuits Group, Hitachi Ltd.
6th Author's Name	Yoshio TAKAMINE
6th Author's Affiliation	Semiconductor & Integrated Circuits Group, Hitachi Ltd.
Date	2003/2/14
Paper #	DC2002-79
Volume (vol)	vol.102
Number (no)	658
Page	pp.pp.-
#Pages	6
Date of Issue