| Presentation | 2002/11/21 Small-Area Multi-Port Register Files with Multi-Bank Structure Hiroshi UCHIDA, Yosuke MITANI, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Tetsuo HIRONAKA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Generally, the area of a conventional multi-port memory increases in proportion to the 2nd power of the number of ports. Therefore, it is difficult to realize high-speed access and high integration density at the same time. To solve this problem for the register file of highly parallel processors, which generally needs many ports, we propose the application of a hierarchical bank structure (HMA). The new register file architecture realizes the coexistence of small layout size and high-speed access by applying memory banks which internally consist of small 1-port memory cells. In this paper, we compare a conventional multi-port register file and an HMA register file for a 4 issue processor, designed in the same 0.35μm CMOS technology. By applying the renaming and the forwarding technique, the number of banks required for the HMA register file could be reduced to just 4. The final design comparison shows that a 12-port HMA register file with 128 registers has drastically increased cost/perfomance. It realizes about the same access time, but has 24% shorter cycle time and 72% smaller area than its conventional counterpart. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | register file / multi-port memory / hierarchical architecture / bank structure / multiple-issue processor |
| Paper # | DC2002-63 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Small-Area Multi-Port Register Files with Multi-Bank Structure |
| Sub Title (in English) | |
| Keyword(1) | register file |
| Keyword(2) | multi-port memory |
| Keyword(3) | hierarchical architecture |
| Keyword(4) | bank structure |
| Keyword(5) | multiple-issue processor |
| 1st Author's Name | Hiroshi UCHIDA |
| 1st Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University() |
| 2nd Author's Name | Yosuke MITANI |
| 2nd Author's Affiliation | Faculty of Computer Sciences, Hiroshima City University |
| 3rd Author's Name | Hans Jurgen MATTAUSCH |
| 3rd Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 4th Author's Name | Tetsushi KOIDE |
| 4th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 5th Author's Name | Tetsuo HIRONAKA |
| 5th Author's Affiliation | Faculty of Computer Sciences, Hiroshima City University |
| Date | 2002/11/21 |
| Paper # | DC2002-63 |
| Volume (vol) | vol.102 |
| Number (no) | 479 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |