| Presentation | 2002/11/21 The Width Constrained Placement by the Simulated Annealing with the Sequence-Pair Encoding Satoshi TAYU, Mineo KANEKO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The module placement is one of the most important problem in the VLSI design. As the remarkable progress of VLSI technologies in recent years, it becomes harder to compute an area minimized placement effectively. Therefore, in the recent VLSI physical design, stochastic methods come to be employed. One of the most effective stochastic methods for the problem is the simulated annealing approach with sequence-pair encoding. In this paper, we propose a penalty function approach in a simulated annealing for the vertical width minimization placement problem under horizontal width constraint using sequence-pair encoding, and show its effectiveness by experimental results for a randomly generated module set and MCNC benchmark ami49. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | penalty function / simulated annealing / sequence-pair / width constraint |
| Paper # | DC2002-52 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Width Constrained Placement by the Simulated Annealing with the Sequence-Pair Encoding |
| Sub Title (in English) | |
| Keyword(1) | penalty function |
| Keyword(2) | simulated annealing |
| Keyword(3) | sequence-pair |
| Keyword(4) | width constraint |
| 1st Author's Name | Satoshi TAYU |
| 1st Author's Affiliation | School of Information Science, Japan Advanced Information Science and Technology() |
| 2nd Author's Name | Mineo KANEKO |
| 2nd Author's Affiliation | School of Information Science, Japan Advanced Information Science and Technology |
| Date | 2002/11/21 |
| Paper # | DC2002-52 |
| Volume (vol) | vol.102 |
| Number (no) | 479 |
| Page | pp.pp.- |
| #Pages | 6 |
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