Presentation | 2002/11/21 Logic Synthesis of LUT Cascades with Limited Rails : A Direct Implementation of Multi-Output Functions Alan MISHCHENKO, Tsutomu SASAO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Programmable LUT cascades are used to evaluate multi-output Boolean functions. This paper shows several representations of multi-output functions and introduces a new decomposition algorithm applicable to these representations. The algorithm produces LUT cascades with the limited number of rails, which leads to significantly faster circuits and applicability to large designs. The experiment shows that the proposed algorithm performs well on benchmark functions. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Programmable Logic / Look-Up Table (LUT) / Logic Synthesis / Decomposition / Binary Decision Diagrams |
Paper # | DC2002-51 |
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Committee | DC |
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Conference Date | 2002/11/21(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Logic Synthesis of LUT Cascades with Limited Rails : A Direct Implementation of Multi-Output Functions |
Sub Title (in English) | |
Keyword(1) | Programmable Logic |
Keyword(2) | Look-Up Table (LUT) |
Keyword(3) | Logic Synthesis |
Keyword(4) | Decomposition |
Keyword(5) | Binary Decision Diagrams |
1st Author's Name | Alan MISHCHENKO |
1st Author's Affiliation | Department of ECE, Portland State University() |
2nd Author's Name | Tsutomu SASAO |
2nd Author's Affiliation | Center for Microelectronic Systems and Department of CSE, Kyushu Institute of Technology |
Date | 2002/11/21 |
Paper # | DC2002-51 |
Volume (vol) | vol.102 |
Number (no) | 479 |
Page | pp.pp.- |
#Pages | 6 |
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