| Presentation | 2002/11/21 Basic Design of a Large-Scale Multi-processor Automatic Generation System Noritaka IKEDA, Hideto NISHIKADO, Yoshitaka SETO, Toshiyuki KATO, Hironori YAMAUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed a multi-processor based software and hardware co-design platform intended for generating real-time applications. This system, first, extracts the parallelism automatically from an original program described by C language, and then execute task scheduling to synthesize automatically the net-list of the connection between each PE that has communication ports described in HDL, in order that it can automatically generate both hardware and software of the multi-processor system simultaneously. So far, we have confirmed its work by a simulation in which we conducted an automatic generation of a multi-processor system for an FFT program, which is one of the signal-processing applications. Further, to make the system applicable to larger-scale applications, we have examined a prototype of a large-scale automatic multi-processor generation system on making the network among the processors hierarchical, some improvements in the scheduling part and so on. So we are here reporting that discussion. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Hardware-Software Co-design / Multi-processor system / Parallelizing compiler / System on Chip |
| Paper # | DC2002-49 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Basic Design of a Large-Scale Multi-processor Automatic Generation System |
| Sub Title (in English) | |
| Keyword(1) | Hardware-Software Co-design |
| Keyword(2) | Multi-processor system |
| Keyword(3) | Parallelizing compiler |
| Keyword(4) | System on Chip |
| 1st Author's Name | Noritaka IKEDA |
| 1st Author's Affiliation | Information Science and Systems Engineering, Graduate School of Science & Engineering, RITSUMEIKAN UNIVERSITY() |
| 2nd Author's Name | Hideto NISHIKADO |
| 2nd Author's Affiliation | Information Science and Systems Engineering, Graduate School of Science & Engineering, RITSUMEIKAN UNIVERSITY |
| 3rd Author's Name | Yoshitaka SETO |
| 3rd Author's Affiliation | Information Science and Systems Engineering, Graduate School of Science & Engineering, RITSUMEIKAN UNIVERSITY |
| 4th Author's Name | Toshiyuki KATO |
| 4th Author's Affiliation | Information Science and Systems Engineering, Graduate School of Science & Engineering, RITSUMEIKAN UNIVERSITY |
| 5th Author's Name | Hironori YAMAUCHI |
| 5th Author's Affiliation | Information Science and Systems Engineering, Graduate School of Science & Engineering, RITSUMEIKAN UNIVERSITY |
| Date | 2002/11/21 |
| Paper # | DC2002-49 |
| Volume (vol) | vol.102 |
| Number (no) | 479 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |