Presentation 2002/11/21
A Seed Selection Procedure for Random Pattern Generators Based on LFSR
Kenichi ICHINO, Ko-ichi WATANABE, Masayuki ARAI, Satoshi FUKUMOTO, Kazuhiko IWASAKI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BIST. By setting the computed seed as an initial value, target fault coverage, for example 100%, can be accomplished with minimum test length. We can also maximize fault coverage for a given test length. Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representation over GF(2^m), where m is the number of LFSR stages. The results show that the test lengths the selected seeds derive are about sixty percent shorter than those derived by conventionally selected seeds for a given fault coverage. We also show that the seeds obtained through this technique accomplish higher fault coverage than the conventional selection procedure. In term of the c7552 benchmark, taking a test-per-scan architecture with a 20-bit LFSR as an example, the number of undetected faults can be decreased from 304 to 227 for 10,000 LFSR patterns using our proposed technique.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) LFSR / BIST / PRPG / Seed
Paper # DC2002-42
Date of Issue

Conference Information
Committee DC
Conference Date 2002/11/21(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Seed Selection Procedure for Random Pattern Generators Based on LFSR
Sub Title (in English)
Keyword(1) LFSR
Keyword(2) BIST
Keyword(3) PRPG
Keyword(4) Seed
1st Author's Name Kenichi ICHINO
1st Author's Affiliation Graduate School of Engineering, Tokyo Metropolitan University()
2nd Author's Name Ko-ichi WATANABE
2nd Author's Affiliation Graduate School of Engineering, Tokyo Metropolitan University
3rd Author's Name Masayuki ARAI
3rd Author's Affiliation Graduate School of Engineering, Tokyo Metropolitan University
4th Author's Name Satoshi FUKUMOTO
4th Author's Affiliation Graduate School of Engineering, Tokyo Metropolitan University
5th Author's Name Kazuhiko IWASAKI
5th Author's Affiliation Graduate School of Engineering, Tokyo Metropolitan University
Date 2002/11/21
Paper # DC2002-42
Volume (vol) vol.102
Number (no) 479
Page pp.pp.-
#Pages 6
Date of Issue