| Presentation | 2002/11/21 Hierarchical BIST : Test-Per-Clock BIST with Low Overhead Ken-ichi YAMAGUCHI, Michiko INOUE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a DFT method for hierarchical BIST for RTL circuits. In the hierarchical BIST approach the fault coverage is the same as when the TPG and RA are directly connected to each of the combinational module. We consider the testability on each combinational module under test (MUT) at gate level, and explore the propagation paths from TPG to MUT and the justification paths from MUT to RA at register transfer level(RTL). The advantage of these methods are that they achieve high fault coverage and lower hardware overhead than other related methods. In this paper, we propose a new testability for hierarchical BIST, time division concurrent single control testability to reduce test application time and hardware overhead. Experimental results are presented to demonstrate the effectiveness of our new approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | design for testability / register transfer level / built-in self test / concurrent single-control testability |
| Paper # | DC2002-39 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hierarchical BIST : Test-Per-Clock BIST with Low Overhead |
| Sub Title (in English) | |
| Keyword(1) | design for testability |
| Keyword(2) | register transfer level |
| Keyword(3) | built-in self test |
| Keyword(4) | concurrent single-control testability |
| 1st Author's Name | Ken-ichi YAMAGUCHI |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Michiko INOUE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2002/11/21 |
| Paper # | DC2002-39 |
| Volume (vol) | vol.102 |
| Number (no) | 479 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |