| Presentation | 2002/11/21 Design for Consecutive Transparency of RTL Circuits Tomokazu YONEDA, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a design-for-consecutive-transparency method that makes a core(RTL circuit) consecutively transparent using integer linear programming. Consecutive transparency of a core guarantees consecutive propagation of arbitrary test/response sequences from the core inputs to the core outputs with some latency. Therefore, it is possible to apply/observe arbitrary test/response sequences to/from an embedded core consecutively at the speed of system clock by using interconnects and consecutively transparent cores in an SoC. Experimental results show that the proposed method introduces lower area overhead compared to the bypass method that adds direct paths from PIs to POs with multiplexers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design for Testability / Systems-on-a-Chip / Test Access Mechanism / Consecutive Transparency / Consecutive Testability / Register Transfer Level |
| Paper # | DC2002-37 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2002/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design for Consecutive Transparency of RTL Circuits |
| Sub Title (in English) | |
| Keyword(1) | Design for Testability |
| Keyword(2) | Systems-on-a-Chip |
| Keyword(3) | Test Access Mechanism |
| Keyword(4) | Consecutive Transparency |
| Keyword(5) | Consecutive Testability |
| Keyword(6) | Register Transfer Level |
| 1st Author's Name | Tomokazu YONEDA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Hideo FUJIWARA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2002/11/21 |
| Paper # | DC2002-37 |
| Volume (vol) | vol.102 |
| Number (no) | 479 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |