Presentation 2002/11/21
A Fault-Tolerance Mechanism for Microprocessors Utilizing Instruction Redundancy
Toshinori SATO, Itsujiro ARITA,
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Abstract(in English) This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller transistors, higher and higher clock frequency, and lower and lower power supply voltage reduce reliability of microprocessors. In addition, microprocessors are used in systems which require high dependability, such as e-commerce businesses. Based on these trends, it is expected that the quality with respect to reliability will become important as well as performance and cost for future microprocessors. To meet the demand, we have proposed and evaluated a fault-tolerance mechanism, which is based on instruction reissue and utilizes time redundancy, and found severe performance loss. In order to mitigate the loss, this paper proposes to exploit instruction redundancy. Using the reuse table, previously executed computing is reused for checking the occurrence of transient faults. From detailed simulations, we find that the performance loss caused by introducing fault-tolerance into 4-way and 8-way superscalar processors is 12.5% and 20.8%, respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) fault-tolerance / instruction reuse / transient faults / time redundancy / instruction reissue
Paper # DC2002-36
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Committee DC
Conference Date 2002/11/21(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Fault-Tolerance Mechanism for Microprocessors Utilizing Instruction Redundancy
Sub Title (in English)
Keyword(1) fault-tolerance
Keyword(2) instruction reuse
Keyword(3) transient faults
Keyword(4) time redundancy
Keyword(5) instruction reissue
1st Author's Name Toshinori SATO
1st Author's Affiliation Department of Artificial Intelligence, Kyushu Institute of Technology:Center for Microelectronic Systems, Kyushu Institute of Technology()
2nd Author's Name Itsujiro ARITA
2nd Author's Affiliation Department of Artificial Intelligence, Kyushu Institute of Technology
Date 2002/11/21
Paper # DC2002-36
Volume (vol) vol.102
Number (no) 479
Page pp.pp.-
#Pages 6
Date of Issue