| Presentation | 2003/5/14 MPLS label switching router implementation enhanced with Network Processor Rinne WATANABE, Satoshi UDA, Nobuo OGASHIWA, Yojiro UO, Yoichi SHINODA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The type of software router has very high flexibility and functional extensibility, whereas it has much lower performance and less wide application than the exclusive hardware router in many case. Development and utilization of the processor optimized for the network processing (NP) has attracted much attention as one of techniques to decrease a performance gap between software and hardware routers. When outside NP module handle a part of existing network stack functions, whole system can be made faster without little damage to the flexibility of software implementations. This paper discusses about the design and implementation of the hybrid router with the IXP1200 intel network processor on generic PC to improve the forwarding performance of the AYAME software MPLS router. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network Processor / Performance Tuneing / MPLS Router / Software Router |
| Paper # | IA2003-13 |
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| Conference Information | |
| Committee | IA |
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| Conference Date | 2003/5/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Internet Architecture(IA) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | MPLS label switching router implementation enhanced with Network Processor |
| Sub Title (in English) | |
| Keyword(1) | Network Processor |
| Keyword(2) | Performance Tuneing |
| Keyword(3) | MPLS Router |
| Keyword(4) | Software Router |
| 1st Author's Name | Rinne WATANABE |
| 1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology:(Present address)Global IP Network Systems Division, Hitachi, Ltd.() |
| 2nd Author's Name | Satoshi UDA |
| 2nd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology |
| 3rd Author's Name | Nobuo OGASHIWA |
| 3rd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology |
| 4th Author's Name | Yojiro UO |
| 4th Author's Affiliation | Research Laboratory, Internet Initiative Japan Inc. |
| 5th Author's Name | Yoichi SHINODA |
| 5th Author's Affiliation | Center for Information Science, Japan Advanced Institute of Science and Technology |
| Date | 2003/5/14 |
| Paper # | IA2003-13 |
| Volume (vol) | vol.103 |
| Number (no) | 62 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |