| Presentation | 2004/2/27 Development of an 80 Gbps Combined Input-Output Queued Packet Switch with 10 Gbps Interfaces Hirotoshi YAMADA, Hiroshi NAKAMURA, Ryuichi KITAICHI, Shinji FURUYA, Takao KATSUTA, Nobuyuki KOBAYASHI, Toshihiro SHIKAMA, Kazuyoshi OSHIMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a new high-throughput, low-cost and non-blocking (work-conserving) packet switching architecture based on the combined input-output queuing, which is code-named "SPRING". It employs large input buffers, small output buffers and a centralized scheduler superior in traffic control functions. As the system performance is heavily dependent on a scheduling algorithm adopted by the scheduler, we propose a new scheduling algorithm "Fewer-Candidates Selected-First (FCSF) scheduling algorithm" to achieve high throughput. This paper also reports implementation of the switch chip based on SPRING architecture using CMOS technology and a prototype of an IP switching node, which offers 80 Gbps switching capacity with 10 Gbps line interfaces. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | lOGbps / Combined Input-Output Queued / Packet Switch / Scheduling Algorithm |
| Paper # | NS2003-376,IN2003-331 |
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| Conference Information | |
| Committee | NS |
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| Conference Date | 2004/2/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Network Systems(NS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of an 80 Gbps Combined Input-Output Queued Packet Switch with 10 Gbps Interfaces |
| Sub Title (in English) | |
| Keyword(1) | lOGbps |
| Keyword(2) | Combined Input-Output Queued |
| Keyword(3) | Packet Switch |
| Keyword(4) | Scheduling Algorithm |
| 1st Author's Name | Hirotoshi YAMADA |
| 1st Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hiroshi NAKAMURA |
| 2nd Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 3rd Author's Name | Ryuichi KITAICHI |
| 3rd Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 4th Author's Name | Shinji FURUYA |
| 4th Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 5th Author's Name | Takao KATSUTA |
| 5th Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 6th Author's Name | Nobuyuki KOBAYASHI |
| 6th Author's Affiliation | Electronic Systems Group, Mitsubishi Electric Corporation |
| 7th Author's Name | Toshihiro SHIKAMA |
| 7th Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 8th Author's Name | Kazuyoshi OSHIMA |
| 8th Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| Date | 2004/2/27 |
| Paper # | NS2003-376,IN2003-331 |
| Volume (vol) | vol.103 |
| Number (no) | 690 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |