Presentation | 2004/2/27 DMFQ: Packet Discarding Scheme Improving the Fairness per Flow and its Hardware Design Norio YAMAGAKl, Hideki TODE, Koso MURAKAMI, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Department of Information Networking, Graduate School of Information Science and Technology, Osaka University Yamadaoka 2-1, Suita-shi, Osaka, 565-0871 Japan E-mail: f{yamagaki,tode,murakami}@ist.osaka-u.ac.jp Abstract Various kinds of traffic have been increasing as broadband networks have been deployed recently. Thus, the realization of QoS guarantee for each traffic is a main technical challenge. As one of means to realize QoS guarantee, it is effective that routers have some high-speed and flow-based control mechanisms. So far, to achieve the fairness improvement per flow and high-speed processing, we have proposed the packet discarding scheme, DMFQ (Dual Metrics Fair Queueing). In this paper, we show the algorithm and clarify the effectiveness of DMFQ through simulation. Moreover, we propose the method to implement DMFQ with hardware and show the design results. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | router / packet discarding control / flow succession time / flow management / hardware design |
Paper # | NS2003-297,IN2003-252 |
Date of Issue |
Conference Information | |
Committee | NS |
---|---|
Conference Date | 2004/2/27(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Network Systems(NS) |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | DMFQ: Packet Discarding Scheme Improving the Fairness per Flow and its Hardware Design |
Sub Title (in English) | |
Keyword(1) | router |
Keyword(2) | packet discarding control |
Keyword(3) | flow succession time |
Keyword(4) | flow management |
Keyword(5) | hardware design |
1st Author's Name | Norio YAMAGAKl |
1st Author's Affiliation | Department of Information Networking, Graduate School of Information Science and Technology, Osaka University() |
2nd Author's Name | Hideki TODE |
2nd Author's Affiliation | Department of Information Networking, Graduate School of Information Science and Technology, Osaka University |
3rd Author's Name | Koso MURAKAMI |
3rd Author's Affiliation | Department of Information Networking, Graduate School of Information Science and Technology, Osaka University |
Date | 2004/2/27 |
Paper # | NS2003-297,IN2003-252 |
Volume (vol) | vol.103 |
Number (no) | 690 |
Page | pp.pp.- |
#Pages | 4 |
Date of Issue |