| Presentation | 2003/9/12 P-Gear : A Network Processor Architecture for Next Generation Internet Hiroaki NISHI, Michitaka OKUNO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A fine-grain large-bandwidth communication, demanded future ubiquitous environment using high-speed Ethernet, requires the break-through of a router architecture. Tera-Gears are new router architectures supporting such a communication. In this report, a part of Tera-Gears, P-Gear is described. P-Gear is a network processor architecture consisting of Header Learning Cache and Header Reissue Handler for using localities of network traffic. They enable to forward a packet without an execution on a PU (Processing Unit) when the packet is needed a same process and the process was recently done by the PU. Therefore, P-Gear attains the fine-grain large-bandwidth communication because of its effective packet processing. Moreover Header Reissue Handler supports effective Header Learning Cache utilization and in-order packet forwarding. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Next-generation Router / Network Processor / Header Learning Cache / Header Reissue Handler |
| Paper # | NS2003-121 |
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| Conference Information | |
| Committee | NS |
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| Conference Date | 2003/9/12(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Network Systems(NS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | P-Gear : A Network Processor Architecture for Next Generation Internet |
| Sub Title (in English) | |
| Keyword(1) | Next-generation Router |
| Keyword(2) | Network Processor |
| Keyword(3) | Header Learning Cache |
| Keyword(4) | Header Reissue Handler |
| 1st Author's Name | Hiroaki NISHI |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Michitaka OKUNO |
| 2nd Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| Date | 2003/9/12 |
| Paper # | NS2003-121 |
| Volume (vol) | vol.103 |
| Number (no) | 310 |
| Page | pp.pp.- |
| #Pages | 4 |
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