Presentation 2003/9/12
Hardware Design of the Flow-based Packet Discarding Control Mechanism
Norio YAMAGAKI, Hideki TODE, Koso MURAKAMI,
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Abstract(in English) In the future IP networks, the main technical issue will be to guarantee QoS for various traffic. In particular, in order to realize flexible QoS guarantee and more broadband networks, the high-speed and flow-based control mechanism will be required. So far, we have proposed the packet discarding scheme considering flow succession time to improve the unfairness per flow and guarantee the QoS. Also, we have confirmed the effectiveness of our proposal method through the simulation results. In this paper, we implement our proposal method with hardware. Concretely, we propose the design policy, and show the hardware design results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) router / packet discarding control / flow succession time / flow management / hardware design
Paper # NS2003-119
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Committee NS
Conference Date 2003/9/12(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware Design of the Flow-based Packet Discarding Control Mechanism
Sub Title (in English)
Keyword(1) router
Keyword(2) packet discarding control
Keyword(3) flow succession time
Keyword(4) flow management
Keyword(5) hardware design
1st Author's Name Norio YAMAGAKI
1st Author's Affiliation Department of Information Networking, Graduate School of Information Science and Technology, Osaka University()
2nd Author's Name Hideki TODE
2nd Author's Affiliation Department of Information Networking, Graduate School of Information Science and Technology, Osaka University
3rd Author's Name Koso MURAKAMI
3rd Author's Affiliation Department of Information Networking, Graduate School of Information Science and Technology, Osaka University
Date 2003/9/12
Paper # NS2003-119
Volume (vol) vol.103
Number (no) 310
Page pp.pp.-
#Pages 4
Date of Issue