Presentation 2004/2/24
Railway Interlocking Safety Verification and its Simulator Based on EVALPSN
Kazumi Nakamatsu, Yosuke Kiuchi, Atsuyuki Suzuki,
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Abstract(in English) Railway operation disorder is a serious problem and expected to be recovered as soon as possible, we introduce an EVALPSN (Extended Vector Annotated Logic Program with Strong Negation) based railway interlocking safety verification. We are planning to provide a railway diagram recovery system based EVALPSN with interval temp oral reasoning. The system consists of a railway interlocking safety verification system and a railway diagram simulation system. In this paper, we introduce the ideas of the railway interlocking safety verification system based on EVALPSN and its prototype simulation system with signal control.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Railway Interlocking Safety verification / Annotated logic program / Defeasible deontic reasoning / EVALPSN / interval temporal logic
Paper # ITS2003-121
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Committee ITS
Conference Date 2004/2/24(1days)
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Registration To Intelligent Transport Systems Technology (ITS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Railway Interlocking Safety Verification and its Simulator Based on EVALPSN
Sub Title (in English)
Keyword(1) Railway Interlocking Safety verification
Keyword(2) Annotated logic program
Keyword(3) Defeasible deontic reasoning
Keyword(4) EVALPSN
Keyword(5) interval temporal logic
1st Author's Name Kazumi Nakamatsu
1st Author's Affiliation School of H.E.P. T. Himeji Inst. Of Tech()
2nd Author's Name Yosuke Kiuchi
2nd Author's Affiliation School of Information Shizuoka Univ
3rd Author's Name Atsuyuki Suzuki
3rd Author's Affiliation School of Information Shizuoka Univ
Date 2004/2/24
Paper # ITS2003-121
Volume (vol) vol.103
Number (no) 673
Page pp.pp.-
#Pages 8
Date of Issue