| Presentation | 2019-01-31 An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We are developing and researching a common platform for high performance stream computing with Field Programmable Gate Array (FPGA). User APIs and hardware modules for the common platform are developed based on Intel Acceleration Stack (IAS). Intel PAC and OPAE are a hardware part and software part of IAS, respectively. In this presentation, an preliminary evaluation of the platform and the current status of our research are shown. We implemented two Direct Memory Access Controller (DMAC) modules and a Lattice-Boltzmann Method (LBM) computing core, a computational fluid dynamics application, on Intel PAC. A control software for DMAC modules and LBM core is developed as well. We evaluated four designs of LBM core and observed that the sustained performance of each design is the same as the theoretical peak performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | LBM / FPGA Cluster / DMAC |
| Paper # | VLD2018-92,CPSY2018-102,RECONF2018-66 |
| Date of Issue | 2019-01-23 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2019/1/30(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Masato Motomura(Hokkaido Univ.) / Noriyuki Minegishi(Mitsubishi Electric) / Koji Nakano(Hiroshima Univ.) / Koji Inoue(Kyushu Univ.) |
| Vice Chair | / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) |
| Secretary | (NEC) / Yuichiro Shibata(Kochi Univ. of Tech.) / Kentaro Sano(NTT) / Nozomu Togawa(Hiroshima City Univ.) / Hidetsugu Irie(e-trees.Japan) / Takashi Miyoshi(NTT) / (Univ. of Aizu) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card |
| Sub Title (in English) | |
| Keyword(1) | LBM |
| Keyword(2) | FPGA Cluster |
| Keyword(3) | DMAC |
| 1st Author's Name | Takaaki Miyajima |
| 1st Author's Affiliation | RIKEN R-CCS(RIKEN) |
| 2nd Author's Name | Tomohiro Ueno |
| 2nd Author's Affiliation | RIKEN R-CCS(RIKEN) |
| 3rd Author's Name | Kentaro Sano |
| 3rd Author's Affiliation | RIKEN R-CCS(RIKEN) |
| Date | 2019-01-31 |
| Paper # | VLD2018-92,CPSY2018-102,RECONF2018-66 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-430,CPSY-431,RECONF-432 |
| Page | pp.pp.125-130(VLD), pp.125-130(CPSY), pp.125-130(RECONF), |
| #Pages | 6 |
| Date of Issue | 2019-01-23 (VLD, CPSY, RECONF) |