| Presentation | 2019-01-30 An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set for n multiple faults, only the additional test patterns for the undetected faults by the existing test patterns for n - 1 multiple faults are generated. Moreover, by introducing an efficient fault selection method, the size of the fault list to be dealt with isreduced drastically compared to the entire fault list of n multiple faults. Our experimental results on ISCAS benchmarks up to triple faults indicates that the proposed method can generate a compact test set to cover all the faults within an acceptable runtime. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2018-74,CPSY2018-84,RECONF2018-48 |
| Date of Issue | 2019-01-23 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | IPSJ-SLDM / RECONF / VLD / CPSY / IPSJ-ARC |
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| Conference Date | 2019/1/30(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yutaka Tamiya(Fujitsu Lab.) / Masato Motomura(Hokkaido Univ.) / Noriyuki Minegishi(Mitsubishi Electric) / Koji Nakano(Hiroshima Univ.) / Koji Inoue(Kyushu Univ.) |
| Vice Chair | / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Nozomu Togawa(Waseda Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) |
| Secretary | (NEC) / Yuichiro Shibata(Kochi Univ. of Tech.) / Kentaro Sano(NTT) / Nozomu Togawa(Hiroshima City Univ.) / Hidetsugu Irie(e-trees.Japan) / Takashi Miyoshi(NTT) / (Univ. of Aizu) |
| Assistant | / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) |
| Paper Information | |
| Registration To | Special Interest Group on System and LSI Design Methodology / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Special Interest Group on System Architecture |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults |
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| 1st Author's Name | Peikun Wang |
| 1st Author's Affiliation | The University of Tokyo(UTokyo) |
| 2nd Author's Name | Amir Masoud Gharehbaghi |
| 2nd Author's Affiliation | The University of Tokyo(UTokyo) |
| 3rd Author's Name | Masahiro Fujita |
| 3rd Author's Affiliation | The University of Tokyo(UTokyo) |
| Date | 2019-01-30 |
| Paper # | VLD2018-74,CPSY2018-84,RECONF2018-48 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-430,CPSY-431,RECONF-432 |
| Page | pp.pp.13-18(VLD), pp.13-18(CPSY), pp.13-18(RECONF), |
| #Pages | 6 |
| Date of Issue | 2019-01-23 (VLD, CPSY, RECONF) |