| Presentation | 2019-01-18 Instantaneous Power-Line Frequency Synchronized Superimposed Chart of PLC System Hiroshi Gotoh, Wataru Abe, Ryo Uemura, Kita Kenji, Hiroyasu Ishikawa, Hideyuki Shinonaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | PLC (Power Line Communications) is a communication technology using a power line as a transmission medium. In the previous study, the authors have indicated that a communication forbidden time which is a packet non-detection occurs when a mobile phone charger is connected to a power-line. Furthermore, we have proposed an instantaneous power-line frequency synchronized superimposed chart and its detailed plotting algorithm as an analysis method. In this paper, packet capture data acquired under test bed with various devices or a power strip to change the distance between PLC adapter and the electric device is also plotted as instantaneous power-line frequency synchronized superimposed chart, and the situation of inter-computer communications by PLC system is analyzed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PLC / UDP / Charger / Communication forbidden time / Instantaneous Power-Line Frequency Synchronized Superimposed Chart / Packet Capture Analysis |
| Paper # | CS2018-104 |
| Date of Issue | 2019-01-10 (CS) |
| Conference Information | |
| Committee | OCS / CS |
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| Conference Date | 2019/1/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nobumoto Ohama Memorial Hall (Ishigaki Island) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Itsuro Morita(KDDI Research) / Hidenori Nakazato(Waseda Univ.) |
| Vice Chair | / Jun Terada(NTT) |
| Secretary | (NTT) / Jun Terada(Furukawa Electric) |
| Assistant | / Kazutaka Hara(NTT) / Kentaro Toyoda(Keio Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Optical Communication Systems / Technical Committee on Communication Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Instantaneous Power-Line Frequency Synchronized Superimposed Chart of PLC System |
| Sub Title (in English) | Part1:Communication Analysis under Test Bed |
| Keyword(1) | PLC |
| Keyword(2) | UDP |
| Keyword(3) | Charger |
| Keyword(4) | Communication forbidden time |
| Keyword(5) | Instantaneous Power-Line Frequency Synchronized Superimposed Chart |
| Keyword(6) | Packet Capture Analysis |
| 1st Author's Name | Hiroshi Gotoh |
| 1st Author's Affiliation | Toyo University(Toyo Univ.) |
| 2nd Author's Name | Wataru Abe |
| 2nd Author's Affiliation | Toyo University(Toyo Univ.) |
| 3rd Author's Name | Ryo Uemura |
| 3rd Author's Affiliation | Toyo University(Toyo Univ.) |
| 4th Author's Name | Kita Kenji |
| 4th Author's Affiliation | Toyo University(Toyo Univ.) |
| 5th Author's Name | Hiroyasu Ishikawa |
| 5th Author's Affiliation | Nihon University(Nihon Univ.) |
| 6th Author's Name | Hideyuki Shinonaga |
| 6th Author's Affiliation | Toyo University(Toyo Univ.) |
| Date | 2019-01-18 |
| Paper # | CS2018-104 |
| Volume (vol) | vol.118 |
| Number (no) | CS-393 |
| Page | pp.pp.93-98(CS), |
| #Pages | 6 |
| Date of Issue | 2019-01-10 (CS) |