| Presentation | 2018-12-05 An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since the convolutional neural network has a high-performance recognition accuracy, it is expected to implement various applications on an embedded vision system. An FPGA can calculate the inference algorithm with low-latency and low power consumption using a specific circuit. In the paper, we propose a tri-state weight, which is a generalization of a low-precision and sparse~(pruning) for CNN weight, to reduce the operation cost and parameters of YOLO. In the first layer, we set a weight ${-1,0,+1}$ as a ternary CNN, while in the other layers, we set a ${-w,0,+w}$ as a sparse weight CNN. We apply an indirect memory access architecture to skip zero part and propose the weight parallel 2D convolutional circuit. It can be applied to the AlexNet based CNN, which has different size kernels. Thus, we design the AlexNet based YOLOv2 to reduce the number of layers toward low-latency computation. In the experiment, the proposed tri-state scheme CNN reduces the 90% of weight parameter. We implement the proposed tri-state weight YOLOv2 on a DE5aNet DDR4 board, which has the Intel Corp. Arria10 GX, by using Intel FPGA SDK for OpenCL. It archived 429.0 frames per second (FPS) on a car and person recognition. Compared with the Intel Corei7 7700, it was 203.3 times faster, and its performance per power efficiency was 190.0 times better. Also, compared with the GeForce GTX 1070 GPU, it was 1.74 times faster, and its power performance efficiency was 2.63 times better. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Intel OpenCL / Object Detection / Tristate YOLOv2 / Convolutional Neural Network / Ternary / Pruning / FPGA |
| Paper # | RECONF2018-35 |
| Date of Issue | 2018-11-28 (RECONF) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2018/12/5(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大) |
| Vice Chair | Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII) |
| Secretary | Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL |
| Sub Title (in English) | |
| Keyword(1) | Intel OpenCL |
| Keyword(2) | Object Detection |
| Keyword(3) | Tristate YOLOv2 |
| Keyword(4) | Convolutional Neural Network |
| Keyword(5) | Ternary |
| Keyword(6) | Pruning |
| Keyword(7) | FPGA |
| 1st Author's Name | Youki Sada |
| 1st Author's Affiliation | Tokyo Institute of Technology(titech) |
| 2nd Author's Name | Masayuki Shimoda |
| 2nd Author's Affiliation | Tokyo Institute of Technology(titech) |
| 3rd Author's Name | Shimpei Sato |
| 3rd Author's Affiliation | Tokyo Institute of Technology(titech) |
| 4th Author's Name | Hiroki Nakahara |
| 4th Author's Affiliation | Tokyo Institute of Technology(titech) |
| Date | 2018-12-05 |
| Paper # | RECONF2018-35 |
| Volume (vol) | vol.118 |
| Number (no) | RECONF-340 |
| Page | pp.pp.7-12(RECONF), |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (RECONF) |