Presentation 2018-12-05
Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA
Kotaro Tamura, Tetsu Narumi,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) The calculation cost of a Radiosity method is huge, since it takes into account the global illumination to produce realistic images. Recently, an FPGA accelerator can be implemented using high level synthesis. However, such arithmetic units are difficult to optimize when high level synthesis is used. In this paper, we developed a heterogeneous system using Zynq SoC to accelerate the Radiosity method, and evaluated the optimization method. Several optimization methods with SDSoC greatly reduced hardware resource and latency without losing accuracy. However, we need to further analyze the bottleneck since the calculation speed of the FPGA is slower than that of the CPU alone.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / High Level Synthesis / SDSoC / 3DCG
Paper # RECONF2018-34
Date of Issue 2018-11-28 (RECONF)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2018/12/5(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Satellite Campus Hiroshima
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2018 -New Field of VLSI Design-
Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大)
Vice Chair Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII)
Secretary Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research)
Assistant / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) High Level Synthesis
Keyword(3) SDSoC
Keyword(4) 3DCG
1st Author's Name Kotaro Tamura
1st Author's Affiliation The University of Electro-Communications(UEC univ.)
2nd Author's Name Tetsu Narumi
2nd Author's Affiliation The University of Electro-Communications(UEC univ.)
Date 2018-12-05
Paper # RECONF2018-34
Volume (vol) vol.118
Number (no) RECONF-340
Page pp.pp.1-6(RECONF),
#Pages 6
Date of Issue 2018-11-28 (RECONF)