| Presentation | 2018-12-06 On the Generation of Random Capture Safe Test Vectors Using Neural Networks Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Excessive capture power consumption at scan testing causes the excessive IR drop and it might cause test-induced yield loss. A low-capture-power test generation method for transition faults based on LOC using fault simulation was proposed to resolve the problem. The method mimics fault propagation path information for capture-safe test vectors which have low launch switching activity in the initial test sets. However, when the number of capture-safe test vectors is smaller, there exists faults which do not have any mimicked capture-safe test vectors. In this paper, we construct neural networks which are constituted from a test vector and state transition information of flip-flops as an input layer, circuit structure information as a middle layer, and capture-safe decision as an output layer. We learn low power properties of random test vectors using the neural network and consider an effective method of random capture-safe test vector generation using the neural network. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | low power testing / capture-safe test vectors / neural network / back propagation methods |
| Paper # | VLD2018-51,DC2018-37 |
| Date of Issue | 2018-11-28 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
|---|---|
| Conference Date | 2018/12/5(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Yutaka Tamiya(Fujitsu Laboratories) / 渡辺 晴美(東海大) / 井上 弘士(九大) |
| Vice Chair | Nozomu Togawa(Waseda Univ.) / Hiroshi Takahashi(Ehime Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(RIKEN) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Hideaki Kimata(NTT) / Kazuya Kodama(NII) |
| Secretary | Nozomu Togawa(NTT) / Hiroshi Takahashi(Aizu Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Takashi Miyoshi(Nihon Univ.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Hideaki Kimata(Toyohashi Univ. of Tech.) / Kazuya Kodama(NTT) / (Panasonic) / (Tohoku Univ.) / (KDDI Research) |
| Assistant | / / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yasuo Kimura(Tokyo Univ. of Tech.) / Hideki Nakazawa(Hirosaki Univ.) / Tomoaki Terasako(Ehime Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Masatoshi Tsuge(Socionext) / Tetsuya Hirose(Kobe Univ.) / Kazuya Hayase(NTT) / Yasutaka Matsuo(NHK) / Hiroe Iwasaki(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the Generation of Random Capture Safe Test Vectors Using Neural Networks |
| Sub Title (in English) | |
| Keyword(1) | low power testing |
| Keyword(2) | capture-safe test vectors |
| Keyword(3) | neural network |
| Keyword(4) | back propagation methods |
| 1st Author's Name | Sayuri Ochi |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Kenichirou Misawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Toshinori Hosokawa |
| 3rd Author's Affiliation | Nihon University(Nihon Univ.) |
| 4th Author's Name | Yukari Yamauchi |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Masayuki Arai |
| 5th Author's Affiliation | Nihon University(Nihon Univ.) |
| Date | 2018-12-06 |
| Paper # | VLD2018-51,DC2018-37 |
| Volume (vol) | vol.118 |
| Number (no) | VLD-334,DC-335 |
| Page | pp.pp.89-94(VLD), pp.89-94(DC), |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (VLD, DC) |